Aspects of the present invention are directed to routing-based pin placement and, more particularly, to routing-based pin placement using pin configurations as anchor points to guide a routing tool.
In very large scale integration (VLSI) and/or other similar chip design processes, integrated circuits are created as a result of a combination of thousands or millions of transistors into a single chip. Successful completion of the VLSI and/or the other similar chip design processes generally requires that the chip design be organized and partitioned into smaller units that are commonly referred to as macros. The macros may themselves be representations of individual cells or macro blocks of cells that have some relationship with one another. The macros are then positioned onto the chip at one or more layers thereof along with chip boundary connections, obstacles and nets in accordance with various optimizing rules. The nets serve to connect the macros and the chip boundary connections with one another while avoiding the obstacles.
Pin assignment or placement processes refer to the placement of pins at the chip boundary connections and the boundaries of the macros. The nets connect to these pins and provide signal communication capabilities between mutually connected features. That is, in a hierarchical flow, pins serve as the interface between the components placed in an interior of a macro and elements outside of the macro (i.e., the chip boundary connections or the other macros) at the top level of the chip design. Typically, the positions of the pins are chosen such that the smallest wire lengths within the macro are achieved while physical top level synthesis is not simultaneously forced to suffer from badly placed pins. The first issue is normally addressed by formulating internal macro wire length as an objective such that the overall design aims to minimize the overall wire length. The second issue is addressed by formulating pin constraints.
In practice, neither issue can be addressed perfectly. Pin locations are typically based on the wire length constraints at the higher level hierarchy, but those are not necessarily optimal pin locations based on wire length constraints at the macro-level of hierarchy.